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<div class="header">
  <div class="summary">
<a href="#pub-attribs">Data Fields</a>  </div>
  <div class="headertitle">
<div class="title">cy_stc_scb_spi_config_t Struct Reference<div class="ingroups"><a class="el" href="group__group__scb.html">SCB          (Serial Communication Block)</a> &raquo; <a class="el" href="group__group__scb__spi.html">SPI (SCB)</a> &raquo; <a class="el" href="group__group__scb__spi__data__structures.html">Data Structures</a></div></div>  </div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>SPI configuration structure. </p>
</div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a4fc24e3daa02dc8a81de14341a954110"><td class="memItemLeft" align="right" valign="top"><a id="a4fc24e3daa02dc8a81de14341a954110"></a>
<a class="el" href="group__group__scb__spi__enums.html#ga931ca8a003e3da524aadd562945d3ab5">cy_en_scb_spi_mode_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#a4fc24e3daa02dc8a81de14341a954110">spiMode</a></td></tr>
<tr class="memdesc:a4fc24e3daa02dc8a81de14341a954110"><td class="mdescLeft">&#160;</td><td class="mdescRight">Specifies the mode of operation. <br /></td></tr>
<tr class="separator:a4fc24e3daa02dc8a81de14341a954110"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a75c45e3e4b63c4bba526de72ac9850ce"><td class="memItemLeft" align="right" valign="top"><a id="a75c45e3e4b63c4bba526de72ac9850ce"></a>
<a class="el" href="group__group__scb__spi__enums.html#ga1410916a9c76b0d86eb196b8e9ed547f">cy_en_scb_spi_sub_mode_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#a75c45e3e4b63c4bba526de72ac9850ce">subMode</a></td></tr>
<tr class="memdesc:a75c45e3e4b63c4bba526de72ac9850ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Specifies the submode of SPI operation. <br /></td></tr>
<tr class="separator:a75c45e3e4b63c4bba526de72ac9850ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7de07d4e2900e6773c541632fecfe611"><td class="memItemLeft" align="right" valign="top"><a id="a7de07d4e2900e6773c541632fecfe611"></a>
<a class="el" href="group__group__scb__spi__enums.html#gab34eae51343cebfec7c447a573cdf0ba">cy_en_scb_spi_sclk_mode_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#a7de07d4e2900e6773c541632fecfe611">sclkMode</a></td></tr>
<tr class="memdesc:a7de07d4e2900e6773c541632fecfe611"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configures the SCLK operation for Motorola sub-mode, ignored for all other submodes. <br /></td></tr>
<tr class="separator:a7de07d4e2900e6773c541632fecfe611"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a49f106ff0d3a5772ff90dd07629ead46"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__scb__spi__enums.html#gaf244ff9c484db24f4935bfec1a397383">cy_en_scb_spi_parity_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#a49f106ff0d3a5772ff90dd07629ead46">parity</a></td></tr>
<tr class="memdesc:a49f106ff0d3a5772ff90dd07629ead46"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configures the SPI parity.  <a href="#a49f106ff0d3a5772ff90dd07629ead46">More...</a><br /></td></tr>
<tr class="separator:a49f106ff0d3a5772ff90dd07629ead46"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a84e4e677ad6df72ecb60a3d399be79b3"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#a84e4e677ad6df72ecb60a3d399be79b3">dropOnParityError</a></td></tr>
<tr class="memdesc:a84e4e677ad6df72ecb60a3d399be79b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the hardware to drop data in the RX FIFO when a parity error is detected.  <a href="#a84e4e677ad6df72ecb60a3d399be79b3">More...</a><br /></td></tr>
<tr class="separator:a84e4e677ad6df72ecb60a3d399be79b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac6a475cbca4d11fc3c339007694e33c4"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#ac6a475cbca4d11fc3c339007694e33c4">oversample</a></td></tr>
<tr class="memdesc:ac6a475cbca4d11fc3c339007694e33c4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Oversample factor for SPI.  <a href="#ac6a475cbca4d11fc3c339007694e33c4">More...</a><br /></td></tr>
<tr class="separator:ac6a475cbca4d11fc3c339007694e33c4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa1b9fcfc4860b02fb7cd17fc49531cc3"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#aa1b9fcfc4860b02fb7cd17fc49531cc3">rxDataWidth</a></td></tr>
<tr class="memdesc:aa1b9fcfc4860b02fb7cd17fc49531cc3"><td class="mdescLeft">&#160;</td><td class="mdescRight">The width of RX data (valid range 4-32).  <a href="#aa1b9fcfc4860b02fb7cd17fc49531cc3">More...</a><br /></td></tr>
<tr class="separator:aa1b9fcfc4860b02fb7cd17fc49531cc3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6c1579d6d98af6a80e6810a98b8d5f26"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#a6c1579d6d98af6a80e6810a98b8d5f26">txDataWidth</a></td></tr>
<tr class="memdesc:a6c1579d6d98af6a80e6810a98b8d5f26"><td class="mdescLeft">&#160;</td><td class="mdescRight">The width of TX data (valid range 4-32).  <a href="#a6c1579d6d98af6a80e6810a98b8d5f26">More...</a><br /></td></tr>
<tr class="separator:a6c1579d6d98af6a80e6810a98b8d5f26"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a951470717fc8f045858bca8588c4659f"><td class="memItemLeft" align="right" valign="top"><a id="a951470717fc8f045858bca8588c4659f"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#a951470717fc8f045858bca8588c4659f">enableMsbFirst</a></td></tr>
<tr class="memdesc:a951470717fc8f045858bca8588c4659f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the hardware to shift out the data element MSB first, otherwise, LSB first. <br /></td></tr>
<tr class="separator:a951470717fc8f045858bca8588c4659f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aad9bb6b5bf1883ecb44ee09398903f47"><td class="memItemLeft" align="right" valign="top"><a id="aad9bb6b5bf1883ecb44ee09398903f47"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#aad9bb6b5bf1883ecb44ee09398903f47">enableFreeRunSclk</a></td></tr>
<tr class="memdesc:aad9bb6b5bf1883ecb44ee09398903f47"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the master to generate a continuous SCLK regardless of whether there is data to send. <br /></td></tr>
<tr class="separator:aad9bb6b5bf1883ecb44ee09398903f47"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4a8fa24b12a399b989276d7c6fa42837"><td class="memItemLeft" align="right" valign="top"><a id="a4a8fa24b12a399b989276d7c6fa42837"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#a4a8fa24b12a399b989276d7c6fa42837">enableInputFilter</a></td></tr>
<tr class="memdesc:a4a8fa24b12a399b989276d7c6fa42837"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables a digital 3-tap median filter to be applied to the input of the RX FIFO to filter glitches on the line. <br /></td></tr>
<tr class="separator:a4a8fa24b12a399b989276d7c6fa42837"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7d9321758074460909ddaf8805f77fd8"><td class="memItemLeft" align="right" valign="top"><a id="a7d9321758074460909ddaf8805f77fd8"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#a7d9321758074460909ddaf8805f77fd8">enableMisoLateSample</a></td></tr>
<tr class="memdesc:a7d9321758074460909ddaf8805f77fd8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the master to sample MISO line one half clock later to allow better timings. <br /></td></tr>
<tr class="separator:a7d9321758074460909ddaf8805f77fd8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae4b3221dd3bc7d51c4200278261ce63c"><td class="memItemLeft" align="right" valign="top"><a id="ae4b3221dd3bc7d51c4200278261ce63c"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#ae4b3221dd3bc7d51c4200278261ce63c">enableTransferSeperation</a></td></tr>
<tr class="memdesc:ae4b3221dd3bc7d51c4200278261ce63c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the master to transmit each data element separated by a de-assertion of the slave select line (only applicable for the master mode) <br /></td></tr>
<tr class="separator:ae4b3221dd3bc7d51c4200278261ce63c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a53fea8be8ff446f4cdbfba9be4d07948"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#a53fea8be8ff446f4cdbfba9be4d07948">ssPolarity</a></td></tr>
<tr class="memdesc:a53fea8be8ff446f4cdbfba9be4d07948"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets active polarity of each SS line.  <a href="#a53fea8be8ff446f4cdbfba9be4d07948">More...</a><br /></td></tr>
<tr class="separator:a53fea8be8ff446f4cdbfba9be4d07948"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad34edde1bbeb56c4aa6c8a4449887897"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#ad34edde1bbeb56c4aa6c8a4449887897">ssSetupDelay</a></td></tr>
<tr class="memdesc:ad34edde1bbeb56c4aa6c8a4449887897"><td class="mdescLeft">&#160;</td><td class="mdescRight">Indicates the SPI SELECT setup delay (between SELECT activation and SPI clock).  <a href="#ad34edde1bbeb56c4aa6c8a4449887897">More...</a><br /></td></tr>
<tr class="separator:ad34edde1bbeb56c4aa6c8a4449887897"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae3ac7c7f20e280f4eb0a433bd0a5c0ca"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#ae3ac7c7f20e280f4eb0a433bd0a5c0ca">ssHoldDelay</a></td></tr>
<tr class="memdesc:ae3ac7c7f20e280f4eb0a433bd0a5c0ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">Indicates the SPI SELECT hold delay (between SPI clock and SELECT deactivation).  <a href="#ae3ac7c7f20e280f4eb0a433bd0a5c0ca">More...</a><br /></td></tr>
<tr class="separator:ae3ac7c7f20e280f4eb0a433bd0a5c0ca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ade78bd095cdc2abc90389b653f072e94"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#ade78bd095cdc2abc90389b653f072e94">ssInterFrameDelay</a></td></tr>
<tr class="memdesc:ade78bd095cdc2abc90389b653f072e94"><td class="mdescLeft">&#160;</td><td class="mdescRight">Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation).  <a href="#ade78bd095cdc2abc90389b653f072e94">More...</a><br /></td></tr>
<tr class="separator:ade78bd095cdc2abc90389b653f072e94"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8bd8054ad4eb5abac5e4e2d77f305a18"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#a8bd8054ad4eb5abac5e4e2d77f305a18">enableWakeFromSleep</a></td></tr>
<tr class="memdesc:a8bd8054ad4eb5abac5e4e2d77f305a18"><td class="mdescLeft">&#160;</td><td class="mdescRight">When set, the slave will wake the device when the slave select line becomes active.  <a href="#a8bd8054ad4eb5abac5e4e2d77f305a18">More...</a><br /></td></tr>
<tr class="separator:a8bd8054ad4eb5abac5e4e2d77f305a18"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a927681bbde837cd791b5079ef7d95fa7"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#a927681bbde837cd791b5079ef7d95fa7">rxFifoTriggerLevel</a></td></tr>
<tr class="memdesc:a927681bbde837cd791b5079ef7d95fa7"><td class="mdescLeft">&#160;</td><td class="mdescRight">When there are more entries in the RX FIFO then this level the RX trigger output goes high.  <a href="#a927681bbde837cd791b5079ef7d95fa7">More...</a><br /></td></tr>
<tr class="separator:a927681bbde837cd791b5079ef7d95fa7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a853b8bf6437e4a60c959f048a5567003"><td class="memItemLeft" align="right" valign="top"><a id="a853b8bf6437e4a60c959f048a5567003"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#a853b8bf6437e4a60c959f048a5567003">rxFifoIntEnableMask</a></td></tr>
<tr class="memdesc:a853b8bf6437e4a60c959f048a5567003"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bits set in this mask will allow events to cause an interrupt (See <a class="el" href="group__group__scb__spi__macros__rx__fifo__status.html">SPI RX FIFO Statuses</a> for the set of constant) <br /></td></tr>
<tr class="separator:a853b8bf6437e4a60c959f048a5567003"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7238f0cb999b242c6aeb8a3c552bf8eb"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#a7238f0cb999b242c6aeb8a3c552bf8eb">txFifoTriggerLevel</a></td></tr>
<tr class="memdesc:a7238f0cb999b242c6aeb8a3c552bf8eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">When there are fewer entries in the TX FIFO then this level the TX trigger output goes high.  <a href="#a7238f0cb999b242c6aeb8a3c552bf8eb">More...</a><br /></td></tr>
<tr class="separator:a7238f0cb999b242c6aeb8a3c552bf8eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a22bfdf22686ed7f0220cb0fd42ec9abf"><td class="memItemLeft" align="right" valign="top"><a id="a22bfdf22686ed7f0220cb0fd42ec9abf"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#a22bfdf22686ed7f0220cb0fd42ec9abf">txFifoIntEnableMask</a></td></tr>
<tr class="memdesc:a22bfdf22686ed7f0220cb0fd42ec9abf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bits set in this mask allow events to cause an interrupt (See <a class="el" href="group__group__scb__spi__macros__tx__fifo__status.html">SPI TX FIFO Statuses</a> for the set of constants) <br /></td></tr>
<tr class="separator:a22bfdf22686ed7f0220cb0fd42ec9abf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aacc86dbc09c7ca10d87a97938d4bb4a0"><td class="memItemLeft" align="right" valign="top"><a id="aacc86dbc09c7ca10d87a97938d4bb4a0"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__spi__config__t.html#aacc86dbc09c7ca10d87a97938d4bb4a0">masterSlaveIntEnableMask</a></td></tr>
<tr class="memdesc:aacc86dbc09c7ca10d87a97938d4bb4a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bits set in this mask allow events to cause an interrupt (See <a class="el" href="group__group__scb__spi__macros__master__slave__status.html">SPI Master and Slave Statuses</a> for the set of constants) <br /></td></tr>
<tr class="separator:aacc86dbc09c7ca10d87a97938d4bb4a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Field Documentation</h2>
<a id="a49f106ff0d3a5772ff90dd07629ead46"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a49f106ff0d3a5772ff90dd07629ead46">&#9670;&nbsp;</a></span>parity</h2>

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          <td class="memname"><a class="el" href="group__group__scb__spi__enums.html#gaf244ff9c484db24f4935bfec1a397383">cy_en_scb_spi_parity_t</a> cy_stc_scb_spi_config_t::parity</td>
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<p>Configures the SPI parity. </p>
<dl class="section note"><dt>Note</dt><dd>This parameter is available for CAT1B, CAT1C and CAT1D devices. </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#a84e4e677ad6df72ecb60a3d399be79b3">&#9670;&nbsp;</a></span>dropOnParityError</h2>

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<p>Enables the hardware to drop data in the RX FIFO when a parity error is detected. </p>
<dl class="section note"><dt>Note</dt><dd>This parameter is available for CAT1B, CAT1C and CAT1D devices. </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ac6a475cbca4d11fc3c339007694e33c4">&#9670;&nbsp;</a></span>oversample</h2>

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<p>Oversample factor for SPI. </p>
<ul>
<li>For the master mode, the data rate is the SCB clock / oversample (the valid range is 4 to 16, when MISO is used; if MISO is not used then the valid range is 2 to 16).</li>
<li>For the slave mode, the oversample value is ignored. The data rate is determined by the SCB clock frequency. </li>
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<h2 class="memtitle"><span class="permalink"><a href="#aa1b9fcfc4860b02fb7cd17fc49531cc3">&#9670;&nbsp;</a></span>rxDataWidth</h2>

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<p>The width of RX data (valid range 4-32). </p>
<p>It must be the same as <a class="el" href="structcy__stc__scb__spi__config__t.html#a6c1579d6d98af6a80e6810a98b8d5f26">txDataWidth</a> except in National sub-mode. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a6c1579d6d98af6a80e6810a98b8d5f26">&#9670;&nbsp;</a></span>txDataWidth</h2>

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<p>The width of TX data (valid range 4-32). </p>
<p>It must be the same as <a class="el" href="structcy__stc__scb__spi__config__t.html#aa1b9fcfc4860b02fb7cd17fc49531cc3">rxDataWidth</a> except in National sub-mode. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a53fea8be8ff446f4cdbfba9be4d07948">&#9670;&nbsp;</a></span>ssPolarity</h2>

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<p>Sets active polarity of each SS line. </p>
<p>This is a bit mask: bit 0 corresponds to SS0 and so on to SS3. 1 means active high, a 0 means active low. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ad34edde1bbeb56c4aa6c8a4449887897">&#9670;&nbsp;</a></span>ssSetupDelay</h2>

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<p>Indicates the SPI SELECT setup delay (between SELECT activation and SPI clock). </p>
<p>'0': With this setting the same timing is generated as in SCB v1 block. 0.75 SPI clock cycles '1': With this setting an additional delay of 1 SPI clock cycle is generated. 1.75 SPI clock cycles Only applies in SPI MOTOROLA submode, when SCLK_CONTINUOUS=0 and oversampling factor&gt;2. </p><dl class="section note"><dt>Note</dt><dd>This parameter is available for CAT1B, CAT1C and CAT1D devices. </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ae3ac7c7f20e280f4eb0a433bd0a5c0ca">&#9670;&nbsp;</a></span>ssHoldDelay</h2>

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<p>Indicates the SPI SELECT hold delay (between SPI clock and SELECT deactivation). </p>
<p>'0': With this setting the same timing is generated as in CAT1A devices. 0.75 SPI clock cycles '1': With this setting an additional delay of 1 SPI clock cycle is generated. 1.75 SPI clock cycles Only applies in SPI MOTOROLA submode, when SCLK_CONTINUOUS=0 and oversampling factor&gt;2. </p><dl class="section note"><dt>Note</dt><dd>This parameter is available for CAT1B, CAT1C and CAT1D devices. </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ade78bd095cdc2abc90389b653f072e94">&#9670;&nbsp;</a></span>ssInterFrameDelay</h2>

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<p>Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation). </p>
<p>'0': With this setting the same timing is generated as in CAT1A devices. 1.5 SPI clock cycles '1': With this setting an additional delay of 1 SPI clock cycle is generated. 2.5 SPI clock cycles Only applies in SPI MOTOROLA submode, when SCLK_CONTINUOUS=0 and oversampling factor&gt;2. </p><dl class="section note"><dt>Note</dt><dd>This parameter is available for CAT1B, CAT1C and CAT1D devices. </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#a8bd8054ad4eb5abac5e4e2d77f305a18">&#9670;&nbsp;</a></span>enableWakeFromSleep</h2>

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<p>When set, the slave will wake the device when the slave select line becomes active. </p>
<p>Note that not all SCBs support this mode. Consult the device datasheet to determine which SCBs support wake from Deep Sleep. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a927681bbde837cd791b5079ef7d95fa7">&#9670;&nbsp;</a></span>rxFifoTriggerLevel</h2>

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<p>When there are more entries in the RX FIFO then this level the RX trigger output goes high. </p>
<p>This output can be connected to a DMA channel through a trigger mux. Also, it controls the <a class="el" href="group__group__scb__spi__macros__rx__fifo__status.html#gaaa87359ee2a7bd8e448ba5417558e8bf">CY_SCB_SPI_RX_TRIGGER</a> interrupt source. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a7238f0cb999b242c6aeb8a3c552bf8eb">&#9670;&nbsp;</a></span>txFifoTriggerLevel</h2>

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<p>When there are fewer entries in the TX FIFO then this level the TX trigger output goes high. </p>
<p>This output can be connected to a DMA channel through a trigger mux. Also, it controls the <a class="el" href="group__group__scb__spi__macros__tx__fifo__status.html#ga09966d868419acdcc1b39a20e168437a">CY_SCB_SPI_TX_TRIGGER</a> interrupt source. </p>

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